A compact design of SEED block cipher

Filippos Pirpilidis,Paris Kitsos,Athanasios Kakarountas

doi:10.1109/meco.2015.7181881

A compact design of SEED block cipher

Filippos Pirpilidis, Paris Kitsos + Show 1 more

https://doi.org/10.1109/meco.2015.7181881

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Publication Date: Jun 1, 2015

Citations: 9

Affiliation: Technological Educational Institute of Western Greece, Technological Educational Institute of the Ionian Islands

#VHDL Language #Implementation Of Block Cipher + Show 8 more

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Abstract

An efficient compact implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves low level in hardware resources, so it is efficient for area constraints applications such as smart cards. The proposed implementation reaches a data throughput of 29.7 Mbps at 111 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation, the Xilinx Artix 7 (xc7a100tl-csg324C) FPGA device was used.

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