Abstract
Analytical model for asymmetric single-electron tunneling transistors (SETTs), in which resistance and capacitance parameters of source/drain junctions are not equal, has been developed. The model is based on the steady-state master equation, takes only the two most-probable charging states into account, and is therefore very simple. Even so, it can accurately reproduce the peculiar behaviors of an asymmetric SETT, such as the skew in the drain current-gate voltage characteristics and the Coulomb staircase in the drain current-drain voltage characteristic. Analytical expressions for the charge in the Coulomb island and the capacitance components of the SETT are also derived according to the same scheme, and it is demonstrated that the model can precisely describe the various aspects of the SETT behavior.
Published Version (
Free)
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
