A combination of wave-pipelining timing methodology and DPTL circuit design technique

Abstract

This paper presents a combination of differential pass transistor logic (DPTL) circuit design technique and wave-pipelining timing methodology. To the best of the authors' knowledge, the wave-pipelining has been applied to the static logic blocks, only. This approach generates some problems that limit the efficiency of overall solution. The DPTL circuit design technique is a relay based logic with features appearing to have a better match with wave-pipelining than standard gate logic. The proposed combination overcomes some limitations and disadvantages of both DPTL and wave-pipelining, resulting in a new design technique that offers advantages in terms of speed, design efforts, noise susceptibility, and power.