A Colored Petri Net model of VHDL

Abstract

There exists a strong necessity for a formal interpretation of VHDL. This paper address this aspect. The formal model used for this purpose are Colored Petri Nets because they can cover all aspects of VHDL. We start from the underlying executable model of VHDL based on interactive processes. The formal model of a VHDL description results from the specification in Petri Net terms of an intermediate model. This consists of the userdefined processes resulting from the elaboration of a VHDL description, the kernel process (VHDL simulator) and the communicating links between them.