Abstract
This paper presents a methodology for hardware-software co-design. It is based on the formal description technique LOTOS in the specification phase, and on estimation methods at different levels of abstraction in the partitioning phase. The LOTOS specification describes the system as a set of interacting communicating processes. Our HW-SW partitioning algorithm is guided by communications, performance and area estimates and by the suitability of each process for implementation in hardware or software. A partition is evaluated against the design goals and constraints, first using high-level estimates and then if requirements are met, computing estimates at lower levels of abstraction. If the partition fails, the partitioning model is updated with the new, low-level estimates and a new partition is generated. If it succeeds, the resulting hardware and software specifications are synthesized using existing high-level synthesis tools and compilers.
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