A CNTFET Based Quaternary Ful1 Adder

Abstract

The Adder is one of the most important and basic units of arithmetic logics which is used to design many complex circuits. Till now, all arithmetic circuits are mostly use CMOS circuits for binary logic implementation. Recently Carbon nanotube field effect transistor (CNTFET) has attracted many researchers as its threshold voltage can be varied by changing the diameter of carbon nanotube which makes it useful for designing multivalued logic circuits. Exploring this property of CNTFET, few researchers have designed ternary adders. In this work, first time a Quaternary full adder using CNTFET based of circuit is proposed. The proposed circuit is designed based on the conventional CMOS architecture with utilization of inherent binary nature (0,1) of input carry signal. Since voltage at the output of the dynamic logic circuit is stored on a parasitic capacitance, a quaternary keeper circuit is used to alleviate charge sharing problems. The proposed design of Quaternary full adder circuit is simulated using HSPICE simulator with 14 nm Stanford CNTFET model. This adder consumes 103.18 nw power and has delay of 17.46 psec. This is a first effort to design a quaternary logic adder circuit.