A CMP solution enabling STT-RAM fabrication using via-less process flow

Abstract

As current memory technologies become difficult to fabricate and scaling presents a growing challenge, R&D in Spin Transfer Torque Random Access Memory (STT-RAM) is growing rapidly. However, the complex stack of STT-RAM memory presents unique processing challenges. One of these is chemical mechanical planarization (CMP) of oxide and nitride for via-less top contacts. Unique materials used in STT-RAM fabrication require a selective and uniform planarization process. We evaluate ceria and silica slurries for this STT-RAM CMP process. Our results show that ceria-based slurry enables oxide-to-tantalum polish rate selectivity exceeding 100:1 and uniform planarization across the wafer. Electrical results of a device fabricated at Applied Materials show tunnel magneto-resistance (TMR) of 143% that is less than 10% degradation than the blanket film TMR.