A CMOS Wideband Receiver Resilient to Out-of-Band Blockers Using Blocker Detection and Rejection

Abstract

In this paper, an interferer-tolerant receiver for the first group of ultra-wideband (3.1–4.8 GHz) is presented. The entire system operates in two modes: detecting and receiving. In the detecting mode, the interferers pass through a low-noise amplifier (LNA), a multiplier, a phaser, which is a dispersive delay structure, and a decision circuit, while in the receiving mode, the signal passes through the LNA, three tunable notch filters, a mixer [consisting of a switch, a baseband (BB) transconductance stage, and a transimpedance amplifier], and a BB filter. The blocker detector detects the locations of blockers and reports them to the notch filters of the receiver for rejection. The entire system is integrated in a standard TSMC CMOS 65-nm technology and consumes up to 23.8 and 9.6 mW, in the receiving and detecting modes, respectively, with a 1-V voltage supply. The receiver achieves a simultaneous rejection of up to three out-of-band interferers and maximum out-of-band IIP3 and out-of-band IIP2 of 18.9 and 46 dBm, respectively, using a dynamic blocker detection and rejection technique.