A CMOS voltage buffer with slew-rate enhancement

Abstract

A high slew-rate CMOS voltage buffer has been presented in this article. The slew-rate enhancement is achieved by an embedded driver stage activated by internal nodes in the voltage buffer through capacitive coupling. The capacitive coupling provides one-shot auto-off feature for the driver stage. Therefore, the drive stage can be turned off automatically after activation. The auto-off feature of the proposed driver stage guarantees a reliable operation. The proposed voltage buffer is implemented in a commercial 0.35-μm CMOS technology. The active chip area is 345 μm × 246 μm. The single supply voltage is 3.3 V, and the quiescent current is about 7 μA. When the proposed buffer drives a capacitive load of 220 pF, the measured positive and negative slew rates are 0.714 and 1.548 V/μs, respectively. The improvement corresponds to about 22 times for the positive slew rate and 48 times for the negative slew rate when comparing with the voltage buffer without the proposed the slew-rate enhancement circuit.