A CMOS Stacked-FET Power Amplifier Using PMOS Linearizer with Improved AM-PM

Abstract

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a 0.18-μm silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance (Cgs) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than —40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.