A CMOS Receiver Front-end with Fractional-N PLL Synthesizer for MedRadio Applications

Abstract

A CMOS RF receiver front-end with an integrated fractional-N PLL synthesizer and 25% duty-cycle LO generator is presented for MedRadio applications. The receiver front-end comprises a cascode low-noise amplifier, single-to-differential gmstage, quadrature passive mixer, and trans-impedance amplifiers. The PLL synthesizer generates 1.45-1.95 GHz signal, which is then divided by four to generate 25% duty-cycle non-overlapping I/Q LO signals for improved gain and noise performances of the quadrature passive mixer. Implemented in 65 nm CMOS, the fully integrated receiver operates from a 1-V supply, while dissipating 3.2 and 3.5 mW for the RF front-end and PLL synthesizer, respectively. It achieves the voltage gain of +42.2 dB, the noise figure of 3.3 dB, and the input-referred third-order intercept point (IIP3) of -24 dBm. The low-power consumption, high front-end gain, and full integration with the PLL and LO generator make this receiver well suited for low-power small-form-factor MedRadio applications.