A CMOS Phase Noise Filter With Passive Delay Line and PD/CP-Based Frequency Discriminator

Abstract

A CMOS phase noise filter (PNF) enabled by the passive delay line (DL) and phase detector/charge pump (PD/CP)-based frequency discriminator is proposed. The delay-locked loop and dc offset cancellation loop are embedded in the PNF to achieve fully automatic calibration. The PNF is insensitive to the amplitude noise due to the PD/CP phase extraction feature. With a 20-ns DL, the PNF achieves 10.6/15-dB phase noise suppression with −116.6/−114.9-dBc/Hz phase noise sensitivity at 1-MHz offset in low/high-gain mode, respectively. The suppression offset frequency range is 100 kHz–12 MHz with 9.97–10.087-GHz input frequency range. The phase noise sensitivity improves to −119.9/−123.4 dBc/Hz at 1-MHz offset with the 40/80-ns DL, respectively. The integrated jitter from 10 kHz to 100 MHz is 176/111/85.5 fs with the 20/40/80-ns DL. The PNF is fabricated in a 65-nm CMOS process with the chip area of 1.68 mm $\times 1.5$ mm and power consumption of 102 mW. The PNF provides a new approach to further enhance the phase noise and jitter performance especially at low offset frequencies.