A CMOS logarithmic pipeline A/D converter with a dynamic range of 80 dB

Abstract

ADSL (asymmetrical digital subscriber line) applications requires ADCs with wide dynamic input range, of up to 80 dB. The modulation method employed, 14 bit QAM only needs about 42 dB of signal-to noise ratio (SNR) to achieve a BER of 10/sup -8/. This suggest that a converter with a nonlinear characteristic that achieves an SNR of 42 dB and a dynamic range of 80 dB can be used in this type of applications with the advantage of the reduced number of bits. A logarithmic converter has also the advantage that the output SNR is independent of the statistics of the input signal. The proposed converter is a true logarithmic pipeline architecture, with 9 bits and 80 dB dynamic range. This converter processes the input signal in the same way as a linear converter but in the logarithmic domain. This paper describes the design of a logarithmic pipeline A/D converter that meet the ADSL requirements, implemented in a 0.25 /spl mu/m digital CMOS technology. The converter operates at 10 MS/s with 9 bits, has a dynamic range of 80 dB, with 44.3 dB SNR, and dissipates a power of 478 mW, from a 2.5 V power supply.