Abstract
A CMOS electrically configurable gate array that combines the flexibility, efficiency, extendability, and performance of mask-programmed gate arrays with the convenience of user programmability is described. The implementation is facilitated by a novel two-terminal antifuse programmable element and a configurable interconnect technology. The chip has been fabricated using 2- mu m n-well CMOS technology with two-layer metallization.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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