A CMOS Design Strategy for Bit-Serial Signal Processing

Abstract

We present a summary of the features and successes of a Silicon Compiler (FIRST) for LSI nMOS bit-serial signal processors. A replacement cell library of CMOS operators has been designed for the compilation of true VLSI bit-serial signal processors. The cell library is implemented in 2.5-/spl mu/m buIk CMOS technology, and maintains a consistent performance of 20 MHz. We describe the design philosophy and style behind the CMOS cells, detailing the dynamic logic style used, its layout and testability. As an example of the capability of the library, we discuss a full-precision complex multiplier.