A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps

Abstract

This paper presents a variable delay line DLL circuit implemented in a 0.8 /spl mu/m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The DLL circuit is capable of reducing clock skew from 1-3 ns to below 500 ps for clock frequencies from 50 Mhz to 150 Mhz.