A CMOS baseline holder (BLH) for readout ASICs

Abstract

As a result of a cooperation between Brookhaven National Laboratory and eV Products a generation of high performance readout ASICs was developed. One of the novel circuit solutions implemented in the ASICs is the baseline holder (BLH), a system which provides setting and stabilization of the output baseline both at low frequency and at high rate operation. The BLH is conceptually different from the baseline restorer (BLR). With a output peaking voltage 2 V (10 fC), a peaking time 400 ns and a rate 500 kHz, an asymptotic shift of the baseline <8 mV was measured in the periodic case. A resolution higher than 12 bit was found in the random arrival of pulses case.