A CMOS Based Self Repair Fault Tolerant Adder for Low Power Biomedical Systems

Abstract

In recent years, processor cores for biomedical signal processing play a vital role for portable devices. The processing unit in the device performs acquisition, feature detection and decision making. The computing algorithm comprises of adders, multipliers, registers, and buffers. Adders are the basic building blocks of multipliers, filters and feature extraction units. Discrete Wavelet transform is one of the important methods used to filter and extract information from biomedical signals which can be one dimensional or multidimensional. Fault avoidance and tolerance have been approached in past for achieving efficient and reliable system. These prevention and tolerance through redundancy can avoid failures. Different redundancies are adopted through information processing, hardware, software and time redundancy. Fault tolerant circuits can improve the efficiency of the biomedical system like DWT cores. The main objective is to design a reconfigurable full adder with self-checking and self-repairing faults for the DWT architecture. This paper presents a proposed FPGA based fault detection and repairing circuit including the fault location. The existing method uses an on-chip based adder which is complex and is less efficient and not suitable for reprogramming. In the proposed design, DWT architecture was designed using the reconfigurable multiplier, fault tolerant adder and Flip Flop. The implementation was carried out in Quartus Tool for different FPGA kits designed with 90nm and 65nm CMOS technology. Parameters like LUT, power dissipation and delay are investigated. The proposed approach is suitable for portable devices.