A CMOS Balun with Common Ground and Artificial Dielectric Compensation Achieving 79.5% Fractional Bandwidth and <2° Phase Imbalance

Abstract

This paper presents a compact on-chip balun with a turn ratio of 1:2 for sub-6 GHz applications. Common ground between the primary and secondary windings is designed by utilizing a short transmission line (T-line) to eliminate the imbalance. To further mitigate the imbalance, float metal conductors are used as a part of primary winding for artificial dielectric compensation. The balun is fabricated by using a standard 130-nm CMOS process. The bandwidth of the proposed balun for $\vert \mathrm{S}_{11}\vert dB is 2.2-5.1 GHz with fractional bandwidth up to 79.5%. In the operational bandwidth, the maximum amplitude and phase imbalance is 1.5 dB and 2°, respectively. The measured insertion loss is 4.8-5.6 dB (including 3 dB splitting loss) within the frequency range from 2.2 to 5.1 GHz.