Abstract
This paper proposes a new multi level of amplitude and pulse width (PW) modulation structure for a 7Gb/s serial link transceiver. This scheme can be implemented in 0.18 m CMOS technology. Applying this technique, 7 bit data is embedded in a symbol time. Therefore the symbol rate is reduced, while the minimum PW is increased. In the proposed structure, the PW is larger than Tb (a conventional NRZ data PW). Therefore, the ISI will be improved. The multiphase output of a five stage ring oscillator VCO in the PLL is used to modulate and demodulate the signal. In PAM modulator block, a current-mode technique is used to increase the rate of data transmission. Serialization of parallel data is established by a current-mode multiplexer. At the receiver part, a novel high-speed comparator is proposed to demodulate the data signal. In addition, to reinforce the incoming signal, a preamplifier with high gain and high bandwidth is proposed. PWAM modulator, which consists of a PWM modulator and a PAM modulator blocks, consumes 71 mW. The receiver block power consumption is about 14 mW.
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