Abstract
The ToPiX ASIC is a custom development for the hybrid pixel sensors of the PANDA experiment Micro Vertex Detector. The ASIC will provide both the time and amplitude informations (via the Time over Threshold technique) of the incoming particle. ToPiX will consist of a matrix of 116 × 110 cells with a pixel size of 100 × 100 μm2, the column readout logic and two 311 Mbit/s serializers. A reduced scale prototype in CMOS 0.13 μm has been designed and tested. The prototype includes eight columns with the full cell analogue and digital circuitry and the end of column readout.
Highlights
The ToPiX ASIC is a custom development for the hybrid pixel sensors of the PANDA experiment Micro Vertex Detector
A simple Time over Theshold (ToT) mechanism is implemented by adding a register and storing the time stamp value at both edges of the comparator signal
The ASIC is designed in a commercial CMOS 0.13 μm technology in order to take benefit of the high integration level of modern technologies and of the intrinsic resistance to radiation in terms of total ionizing dose
Summary
The unique requirements for the electronic readout of the SPDs of the PANDA experiment, mainly related to the absence of a trigger signal, lead to the development of a custom readout ASIC [3]. The current time stamp value is stored into the pixels only when a signal is detected by the preamplifier-comparator chain. Implemented by adding a register and storing the time stamp value at both edges of the comparator signal. This measurement technique has been already succesfully implemented in other ASICs for silicon pixel readout [4]. Albeit LVDS driver can be designed in this technology using 2.5 V compatible transistors, a second power supply would have been required These thick oxide transistors show a much higher threshold voltage shift under irradiation than the standard ones
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