A clock-less implementation of the AES resists to power and timing attacks

Abstract

New cryptanalytical techniques, in particular, power and timing analysis, pose a serious threat to cryptographic devices such as smart cards. By analyzing the power dissipation or timing of encryptions in a device, encrypted information inside can be deduced. The weakness is not in the encryption algorithms themselves, but in their implementations. We show that not even the new advanced encryption standard (AES), when implemented in conventional hardware, is secure from power attacks; a few power samples were enough to deduce the secret key. A new specially designed implementation of the AES on a clock-less dual-rail chip is presented and shown to possess a very considerable improvement against power attacks compared to the conventional design. This implementation is also resistant to timing, fault induction and clock glitch attacks.