Abstract
This paper presents the combination of two back-off efficiency enhancement techniques, the voltage-mode Doherty and the class-G switched-capacitor power amplifier (PA), to achieve efficiency peaking at both 6 and 12 dB back off without introducing the mode-switching glitches present in previous architectures. The proposed technique enables transmission of high peak-to-average-power ratio (PAPR) signals with high efficiency while maintaining excellent linearity. The PA is fabricated in 45-nm CMOS SOI with integrated balun for power combining and matching. At 3.5 GHz a saturated output power of 25.3 dBm is measured with 30.4%/25.3%/17.4% power added efficiency (PAE) at 0/6/12 dB back off. With memoryless, non-adaptive linearization, the PA achieves 19.2% PAE with −35.8 dB error vector magnitude (EVM) while transmitting a 40 MHz 256-QAM 10.1 dB PAPR 802.11ac modulation. Significant efficiency improvement compared to class-B and EVM better than −34 dB is maintained over more than 1 GHz bandwidth.
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