A class of random multiple bits in a byte error correcting (S/sub t/b/EC) codes for semiconductor memory systems

Abstract

Recent high density wide I/O DRAM chips are highly vulnerable to multiple random bit errors. Therefore, correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is likely to upset more than just one bit stored in that chip. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single DRAM chip output are suitable for application in high speed semiconductor memory systems. This paper proposes a class of codes called single t/b-error correcting (S/sub t/b/EC) codes which are capable of correcting random t-bit errors occurring within a single b-bit byte. For the case where the chip data output is 16 bits, i.e., b = 16, the S/sub 3/16/EC code proposed in this paper requires only 16 check bits, that is, only one chip is required for check bits at practical information lengths such as 64, 128 and 256 bits. Furthermore, this S/sub 3/16/EC code is capable of detecting more than 95% of all single 16 bit byte errors at information length 64 bits.