A circuit simulation model for V-groove SiC power MOSFET

Abstract

In this paper, a novel circuit simulation model for V-groove SiC power MOSFET with buried P-layers is proposed. By considering the structure of the MOSFET, bias dependence of on-resistance and the kink in the terminal capacitance are represented in the proposed model. Through experiments using a V-groove SiC MOSFET, it is demonstrated that the proposed model successfully reproduces both I-V and C-V characteristics.