A Chip Scale Atomic Clock Driven Receiver for Multi-Constellation GNSS

Abstract

This paper presents the design and implementation of a Chip Scale Atomic Clock (CSAC) driven dual-channel Digitally Configurable Receiver (DCR) for Global Navigation Satellite Systems (GNSS). The receiver is intended to be used for research applications such as; multipath mitigation, scintillation assessment, advanced satellite clock and spatial frame transformation modelling, Precise Point Positioning (PPP) as well as rapid development and assessment of novel circuits and systems for GNSS receivers. A novel sub-Nyquist sampling (subsampling) receiver architecture incorporating dual-band microstrip RF filters is employed in order to minimize the complexity of the multi-frequency Radio Frequency (RF) front-end. Moreover, the digital receiver incorporates a novel and complexity-reduced Fast Fourier Transform (FFT) core for signal acquisition as well as COordinate Rotation DIgital Computer (CORDIC) cores for the code/carrier discriminators in order to minimize the resource allocation on the FPGA. The receiver also provides easy access to enable adjustment of its internal parameters such as; RF gain, position update rate, tracking channel correlator spacing and code/carrier loop noise bandwidth. Correlator outputs, code/carrier error, Carrier-to-Noise Ratio (C/N0), navigation and RINEX data are provided to the end-user in real-time. This paper collectively highlights and reports on the implementation, test and validation of the novel techniques, elements and approaches in both the RF and digital part of the DCR that comprise the multi-constellation receiver.