Abstract
In the charge pump phase locked loop (CPPLL), the non-ideal characteristics of charge pump are the main causes of the reference spurs. Therefore, reducing the variety of non-ideal characteristics is one of the challenges in the CP design. In this paper, an improved charge pump circuit, based on the TSMC's 0.18μmCMOS process, has been designed and completed. An operational amplifier and self-biasing cascode current mirror and supply-independent reference current source are used in the CP design to make charge and discharge current matched. The charge pump has characteristics of low power consumption, high speed, good linearity, and high current matching.
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