Abstract
Organosilicate glass (OSG) deposited by plasma enhanced chemical vapour deposition (PECVD) is a likely candidate for 65nm node low k interconnect dielectric. Electron beam (e-beam) treatment efficiently stiffens porous PECVD OSG and may enable extension of PECVD OSG beyond the 65 nm node. Charge damage during e-beam exposure should be considered before implementing e-beam treatments for low k dielectrics. The effects of e-beam cathode potential on CMOS transistor threshold voltage and gate dielectric leakage current are investigated using 130nm node CMOS transistors. The impact of e-beam treatments was negligible on devices with 1.7nm gate dielectrics, but can adversely impact the 6.7nm dielectric devices.
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