A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

S Atsumi,K Isobe,T Watanabe,S Kitamura,S Yamada,A Umezawa,M Matsui,M Saito,T Miyaba,S Mori,Y Takano,H Watanabe,T Tanzawa,T Taura,H Shiga

doi:10.1109/4.881211

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

S Atsumi, K Isobe + Show 13 more

https://doi.org/10.1109/4.881211

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Journal: IEEE Journal of Solid-state Circuits	Publication Date: Nov 1, 2000
Citations: 24

Affiliation: Toshiba (Japan)

#NOR Flash EEPROM #NOR Flash + Show 8 more

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Abstract

A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.

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