A Channel Self-Alignment process for High-Voltage VDMOSFETs in 4H-SiC

Abstract

In this paper, we describe a channel self-alignment process to produce High-Voltage VDMOSFETs in 4H-SiC. We use polysilicon as a mask for two injection methods, Because the oxidation rate of polysilicon is different from that of silicon carbide, we can generate a certain thickness of silicon oxide flank wall by controlling the oxidation rate and time. Therefore, there will be a certain distance between the N+ source region and the Pbase region, and this distance is the length of the channel. Obviously, no pattern transfer occurs between the two ion implantation processes, so the channel is self-aligned. As long as the thickness of the side wall is controlled accurately, the channel length of sub-micron can be obtained.