A cellular automata based design of self testable hardware for March C<sup>−</sup>

Abstract

The March tests are extensively used for functional test of SRAMs and DRAMs. This work reports hardware realization of March C to enable high speed detection of faults in memories. It is developed around a special class of cellular automata (CA) with the target to achieve a test structure self testable. The regular structure of CA enables low cost implementation of test logic for the memory chip that is inherently regular in structure. The CA memorizes the status (faulty/non-faulty) of memory words as well as its own defects during read (r0/r1) operation of the March algorithm. The final state of the n-cell CA, employed for the test hardware, indicates the faults (if any) in a memory word or in the test logic. It effectively reduces the overhead of bit by bit comparison of memory words, that is required in a conventional test structure, to take decision on the faults in memory.