Abstract
An LSI ADPCM codec, which is based on the CCITT standard 32 kbit/s algorithm, has been developed. After thoroughly investigating complex CCITT specifications for arithmetic operations, a software controllable custom LSI processor approach is chosen to reduce hardware amount and power dissipation. The processor architecture is optimized for the CCITT algorithm. A reconfigurable pipeline multiplier-normalizer-accumulator circuit is effectively utilized for floating-point multiply-and-add operations in a predictor output calculation, nonlinear PCM to/from linear PCM code conversions, and powers of 2 multiplications used in adaptation logic units. A microinstruction set is chosen to perform efficient binary tree search processing for ADPCM quantization, in addition to performing parallel processing in independent processor resources. The LSI chip, implemented by 2.5 μ CMOS technology, has 8.2 × 7.4 mm die size and dissipates only 90 mW.
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