Abstract
In this note we focus on the empirical results on a case study of parallel JPEG encoding on real FPGA platform, which evaluates and complements Hill & Marty’s findings. A hardware prototype is constructed on FPGA with MicroBlaze processors and JPEG hardware accelerators. Experimental results on this case study demonstrate that the Hill and Marty’s findings reinforces the hardware/software task partitioning for hybrid MPSoC architectures and also provide creditable new insights to scalable homogeneous and heterogeneous FPGA based MPSoC domains.
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