A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores

Abstract

As non-volatile memory (NVM) technologies advance, commercial NVDIMM devices have been made readily available for various computing systems. To efficiently utilize the high-density and high-capacity of NVM, the latest Xeon CPUs support a special <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Memory Mode</i> that turns the DRAM into a last-level (L4) cache and uses NVM as the user-addressable system memory. Unfortunately, Memory Mode often provides low performance, even slower than when only NVM is used without any DRAM cache. According to our analysis, this is due to the inefficient management of a DRAM cache by the integrated memory controller, which results in high miss rates. This paper proposes a new hybrid memory allocator, called TARMAC. By employing intelligent yet lightweight memory management policies at the memory allocator level, TARMAC manages two different types of memory devices more efficiently, achieving 37% higher cache hit rate, 67% higher throughput, and 40% shorter memory latency than the hardware-based Memory Mode, on average. TARMAC exposes memory interfaces compatible with traditional memory allocators, enabling existing software to use TARMAC without any manual modification.