A Cascaded IIR Filter with Optimized Group Delay

Abstract

A 10-bit cascaded infinite impulse response (IIR) low-pass digital filter with optimized group delay is proposed in this paper. By inserting an all-pass equalizer at the output of each stage of the cascaded IIR filter, the variation of the group delay in pass band is reduced, thereby decreasing the output distortion of the filter. The stability of the 10-bit IIR filter is ensured by carefully locating the zeros and poles. With the 1st and 2nd order equalizers for circuit optimization, simulation results from Matlab modeling and circuit design show that, the group delay in the pass-band range of 0 ~100 Hz, is reduced by 28.19% and 49.93%, respectively. Logic synthesis is performed based on 0.18 μm CMOS standard cell, and it is shown that this group delay optimization technique is suitable for system-on-chip applications due to the low power and small size.