Abstract
A carrier-storage-enhanced superjunction (SJ) insulated gate bipolar transistor (CSE-SJ-IGBT) is proposed and investigated. In the CSE-SJ-IGBT, the p-pillar is connected to the Emitter via one diode or two series diodes, which helps to raise the hole quasi-Fermi potential of the p-pillar at the on-state so as to enhance the carrier-storage effect in the drift region (n-pillar and p-pillar) and reduce the on-state voltage (VCE( <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> )). Moreover, the CSE-SJ-IGBT also can turn off rapidly as the conventional SJ-IGBT. Simulation results show that, under turn-off loss (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) of 5 mJ/cm2, VCE( <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of the 1.45-kV rated CSE-SJ-IGBT is as low as 1.07 V, which is 35% and 40% lower than that of the conventional SJ-IGBT and the field stop IGBT, respectively. Besides, the CSE-SJ-IGBT also offers large design freedom for obtaining excellent E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> -VCE(sat) tradeoff.
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