A Capacitor-less Digital LDO using Ripple-Frequency-Adaptive Time-domain Digital Pre-distortion Technique

Abstract

Fine grained power management for modern SoCs is implemented with DC-DC converters cascading LDOs to achieve high power conversion efficiency [1]. Digital LDOs (D-LDO) suit well for modern SoC applications due to their lower dropout voltage and scaling but suffer from poor PSR and slow transient response especially when cascaded after a switching regulator which usually induces large output voltage ripples [2]. Hybrid LDO (H-LDO) was proposed to achieve fast load transient and high PSR [3] by introducing an analog-proportional path. However, the H-LDO suffers from the limited suppression of large supply ripples as a result of the nonlinearity in analog circuits. Furthermore, the heavy analog part is not easily scaled with CMOS technology. In order to address the above-mentioned issues, this paper introduces a D-LDO with ripple-frequency-adaptive time-domain digital-pre-distortion (DPD) scheme to achieve decent suppression of supply ripple. With a 200-mV input ripple swing, the measured output ripple swing is only 9 mV under a 1.98-MHz supply ripple while the clock frequency is 20 MHz. This work demonstrates the possibility and feasibility of digital-domain ripple cancellation for the first time.