A Calibration Scheme for 24–28-GHz Variable-Gain Phase Shifter in 65-nm CMOS

Abstract

This brief presents a 24–28-GHz variable-gain phase shifter (VG-PS) and a geometric-projection-based three-point calibration scheme. The VG-PS achieves a 360° phase-shifting range with a 6-bit resolution and an 8-dB gain-tuning range with a 0.25-dB step size. The proposed calibration scheme achieves the optimal control codes directly from only three measurements to optimize the amplitude and phase precision and saves the need for I/Q calibration. The chip is fabricated in a 65-nm CMOS process, occupies a 0.27-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area, and consumes 31.9 mW. The measured gain is −7.4 dB at 24–28 GHz, and the input 1-dB gain compression point (IP1dB) is 0.27 dBm at 26 GHz. By using the three-point calibration scheme, the measured root-mean-square (rms) amplitude and phase errors across 64 phase states at the maximum gain are improved from 0.8 dB/9° to 0.25 dB/1.4°, respectively. The measured rms amplitude and phase errors across 32 gain states are less than 0.06 dB/0.78°, respectively.