A cache memory with unit tile and line accessibility

Abstract

Ineffective data access of cache memories becomes a bottleneck for efficient 2-dimensional(2-D) data processing such as image processing and matrix multiplication. In order to solve this problem, a cache memory with both unit tile and unit line accessibility, based on 4-level Z-order tiling layout is proposed. Conventional raster scan order access to this layout is enabled by a hardware-base address translation, which can eliminate overhead of address calculation. The proposed cache can access data in parallel in vertical(unit tile) or horizontal(unit line) direction by 4-level Z-order tiling layout and multi-bank cache organization. Unit tile access corresponding to parallel data access in the vertical direction can exploit 2-D locality. Simulation results show that the 4-level Z-order tiling layout provides both less TLB and L1 data cache misses compared with the raster scan order and the Morton order layout in matrix multiplication and LU decomposition, especially at larger matrix size. An LSI chip of the proposed cache combined with a SIMD-based data path was designed in 2.5 × 5mm2 area by using 0.18μm CMOS technology. Under 3.8ns clock period, read and write latency was suppressed to 3 clock cycles of the same as conventional cache memory of an Intel or ARM high-performance processor.