Abstract
Recently, in 3D Chip-Multiprocessors (CMPs), a hybrid cache architecture of SRAM and Non-Volatile Memory (NVM) is generally used to exploit high density and low leakage power of NVM and a low write overhead of SRAM. The conventional access policy does not consider the hybrid cache and cannot make good use of the characteristics of both NVM and SRAM technology. This paper proposes a Cache Fill and Migration policy (CFM) for multi-level hybrid cache. In CFM, data access was optimized in three aspects: Cache fill, cache eviction, and dirty data migration. The CFM reduces unnecessary cache fill, write operations to NVM, and optimizes the victim cache line selection in cache eviction. The results of experiments show that the CFM can improve performance by 24.1% and reduce power consumption by 18% when compared to conventional writeback access policy.
Highlights
Technology scaling has enabled an increasing number of cores on a chip in 3D Chip-Multiprocessors (CMP)
In order to solve these problems, hybrid cache architecture of SRAM and Non-Volatile Memory (NVM) is generally adopted in 3D
This paper proposes a cache fill and migration policy (CFM) for multi-level hybrid cache in 3D
Summary
Technology scaling has enabled an increasing number of cores on a chip in 3D Chip-Multiprocessors (CMP). Wang et al [14] and Khan [15] proposed line placement and migration policy to improve system performance and reduce power consumption overhead. They did not consider data migration between different cache levels. This paper proposes a cache fill and migration policy (CFM) for multi-level hybrid cache in 3D. The CFM analyzes the migration cost in multi-level hybrid cache architecture and proposes two migration principles to minimize the migration cost. The results show that in multi-level hybrid cache architecture, the CFM can achieve performance improvement and power saving effectively.
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