A built‐in testing scheme for ic memories by considering address decoder and cell array separately

Abstract

AbstractIn the built‐in testing of the IC memory, the testing efficiency can be improved by building the testing circuit into the IC memory, that can observe and/or control the part which is difficult or impossible to be observed and/or controlled by the traditional method. From the functional viewpoint, the IC memory can be divided into the address‐part (address decoder, etc.) and the data part (memory cell, etc.). In the traditional testing, the address‐part is tested through the data part. In this paper, a built‐in testing scheme is discussed in which the testing circuit is built in so that the address and the data part can be tested separately. Restricting the faults to be the stuck‐at fault of the address decoder, the stuck‐at fault of the memory cell, and the interference fault by the 1‐neighborhood cells, those faults can be tested by compressing the response by a simple compression function, using the O(N) test sequence (where the sequence length is proportional to the memory capacity N). The test sequence generation circuit and the response compression circuit can be implemented simply by employing counters and shift registers. The extra hardware complexity becomes negligible with the increase of the memory capacity. Thus, it was proved as effective that the testing circuit is built‐in that can observe and/or control the part, which is difficult or impossible to be observed and/or controlled by the traditional method.