A buffered nondestructive-readout Josephson memory cell with three gates

Abstract

The design and testing of a nondestructive readout memory cell with buffer gates to eliminate the half-select problem and to increase the operating margins are described. A 50 mu m*52 mu m cell has been fabricated using a Nb-AlO/sub x/-Nb process with 2.5 mu m line width and 3.75 mu m junction size. The measured margins for data, read-enable, and sense lines are +or-27%, +or-17%, and +or-48%, respectively. Variations of this buffer-gate memory design are also discussed.