Abstract
The level of complexity and the turn-around time associated with the development of custom bipolar VLSI chips have defined the need for a highly structured physical and electrical design validation approach which can guarantee fully functional first-pass chips, yet be flexible enough to allow logical and physical designers the latitude necessary to achieve specified cost and performance objectives. This paper describes such a design verification strategy and its implied constraints on chip design. The rationale for comparing the logic equivalence of the high-level logical models to the low-level-device physical models is presented, a description of the hierarchical logical-to-physical and electrical checking is given, and its impact on cost and complexity is examined.
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