A Binary Integer Decimal-based Multiplier for Decimal Floating-Point Arithmetic

Abstract

Demand for Decimal Floating-Point (DFP) arithmetic is increasing because global business, e-commerce, financial applications, and the standards and laws that govern them require it. The IEEE P754 Draft Standard for Floating-point Arithmetic specifies formats and operations for DFP numbers. In this paper, we present an IEEE P754-compliant multiplier that operates on values that use the binary encoding of DFP numbers, commonly referred to as the Binary Integer Decimal (BID) encoding. Our BID-based DFP multiplier uses high-speed binary hardware, has variable latency, and is optimized for the common case that the product does not need to be rounded. Our multiplier also uses a novel technique that estimates the number of product digits that needed to be rounded in parallel with the significand multiplication. In this design, a single multiplier is used to multiply the significands and round the product. We believe this the first hardware design of a DFP multiplier for BID-encoded numbers.