Abstract
Computation of switching activity is a required step for dynamic power estimation of digital circuits. Switching activity estimation is a difficult task because it not only depends on the circuit structure but also on the input sequence. Probabilistic methods are one of the main approaches for solving this task. These methods frequently resort to binary decision diagrams (BDD) due to their properties; however, BDDs may grow excessively for large and complex circuits. In this paper we propose an optimized BDD structure for activity computation. The resulting BDDs attain significant reductions in the number of nodes without any accuracy loss. The proposal includes an activity operator definition by which the BDD elaboration has been automated and thus, many circuits could be analyzed confirming the theoretical advantages.
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