Abstract
This paper presents a new BiCMOS dynamic carry look ahead circuit (CLA), which is free from race problems, for VLSI implementation of high speed arithmetic unit. Using the BiCMOS dynamic CLA circuit, a 16-bit fdl adder test circuit which has been designed based on a 2pm BiCMOS technology, shows a more than 2 times improvement in speed as compared to the CMOS Manchester CLA circuit. The speed advantage of the BiCMOS dy- namic CLA is even greater in a 32-bit or 64-bit adder, which is very helpful for high speed VLSI CPU de- signs.
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