A Bias-Dependent Single-Event-Enabled Compact Model for Bulk FinFET Technologies

Abstract

A single-event-enabled compact model for bulk FinFET technologies has been developed and integrated with a process design kit (PDK) and an industry standard electronic design automation tool flow. The compact model incorporates transistor bias dependence and 3-D ion-incidence geometry awareness into the calculation of the single-event-generated current waveform. The model has been developed for performance from nominal supply circuit operation down to near-threshold voltage applications. The 3-D technology computer-aided design simulations have been used to calibrate the compact model transient current and voltage waveforms for single, hard-biased, devices and full 3-D logic gate response, e.g., inverter, NAND, and NOR. Single-event transient pulsewidth measurements, from heavy-ion testing over an angle of incidence and bias, on a technology characterization vehicle test chip fabricated at the 14-/16-nm bulk FinFET technology generation, have been used to validate the model response. The bulk FinFET single-event-enabled compact model, integrated with the PDK, enables a single-event analysis of circuit topologies for application in radiation environments while maintaining the standard integrated circuit design flow.