A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3A/mm2 Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS

Abstract

The profile of portable and wearable devices keeps shrinking, demanding high current density power management integrated circuits. Switched-capacitor (SC) converters and buck converters are two common solutions. Unregulated SC converters can achieve high power density and high efficiency for specific voltage conversion ratios (VCRs). However, to cover wide input and output voltage ranges, they require a reconfigurable topology with multiple VCRs, thus increasing the system complexity. On the other hand, buck converters can reach a good efficiency over a wide continuous VCR range. Yet, they need a bulky inductor, which significantly degrades the power density. To address the power density and efficiency tradeoff, hybrid converters composed of both inductor and capacitor are among popular solutions [1 – 4]. When compared with the traditional buck converter, these hybrid converters feature lower voltage swing (smaller current ripple) of the inductor, higher switching frequency, and a larger duty cycle (D) for the same VCR, alleviating the requirements on the inductor, and resulting in higher power density. Nevertheless, as all the output current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf> goes through the inductor, this implies a large volume for small DCR and conduction loss <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${P_{\text{COND}}}$</tex> _ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> . Recently, hybrid converters with reduced inductor current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> have emerged [5 – 7]. In these hybrid converters, the SC not only lowers down the voltage of the switch node, but also offers another current path to the output, reducing the inductor current. In this work, we propose an SC-parallel-inductor buck topology (which we refer to as CPL-Buck since in the proposd structure there is a capacitor that is always in parallel with the inductor) that can further reduce / <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> to less than 0.5I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf> , meaning a P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">COND</inf> _ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> reduction of over 75% for the same DCR. Measurement results show that, for 1.2A maximum I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf> , 3-to-4.2V input to 0.6-to-1V output, the proposed CPL-Buck obtains a peak efficiency of 92.9% and a peak current density of 0.3A/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a power inductor as small as 1.6×0.8×0.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .