A Bandwidth Efficient Turbo Coding Scheme for VDSL Systems

Abstract

The current forward error correction (FEC) scheme for very high bit-rate digital subscriber line (VDSL) systems in the ANSI standard employs a 16-state four-dimensional (4D) Wei code as the inner code and the Reed-Solomon (RS) code as the outer code. The major drawback of this scheme is that further improvement cannot be achieved without a substantial increase in the complexity and power penalty. Also, a VDSL system employing the 4D Wei-RS scheme operates far below the channel capacity. In 1993, powerful turbo codes were introduced whose performance closely approaches the Shannon limit. In this paper, we propose a bandwidth and power efficient turbo coding scheme for VDSL modems in order to obtain high data rates, extended loop reach and increased transmission robustness. We also propose a pipelined decoding scheme to reduce the latency at the receiver end. The objective of the proposed scheme is to provide a higher coding gain than that given by the 4D Wei-RS scheme, resulting in an improved performance of the VDSL modems in terms of bit rate, loop length and transmitting power. The scheme is investigated for various values of transmitting power, signaling frequencies and numbers of crosstalkers for a targeted bit error rate of 10−5 and is implemented in a system with a quadrature amplitude modulation in which a mixed set partitioning mapping is employed to reduce the decoding complexity. The effects of code complexity, interleaver length, the number of decoding iterations and the level of modulation on the performance of VDSL modems are explored. Simulation results are presented and compared to those of the 4D Wei-RS scheme. The results show that the choice of turbo codes not only provides a significant coding gain over the standard FEC scheme but also efficiently maximizes the loop length and bit rate at a very low transmitting power in the presence of dominant far-end crosstalk and intersymbol interference. In order to compare the hardware complexity, we synthesize the proposed and 4D Wei-RS schemes using SYNOPSYS with the target technology of Xilinx 4020e-3. The Xilinx field programmable gate array statistics of the proposed scheme is compared with that of the 4D Wei-RS scheme.