A band-limited CPWL-based memory polynomial model for digital predistortion

Abstract

With the development of mobile communications, the wideband radio frequency (RF) power amplifier (PAs) with high linearity have been an important research field. Digital predistortion (DPD) is an essential solution and it plays an important role in improving linearity of PAs. In this paper, a band-limited canonical piecewise-linear function (CPWL)-based memory polynomial (MP) model is proposed for wideband PAs. The proposed model has a low complexity because the high-order terms of the band-limited MP model are replaced by the CPWL functions. By the band-limited approach, the sampling rate of analog to digital converters (ADCs) and digital to analog converters (DACs) can be reduced. Experimental results show that the proposed model can achieve nearly the same performance of the band-limited second-order simplified DDR model and the band-limited memory polynomial model when a wideband power amplifier is excited by a 5-carrier long-term evolution advanced (LTE-A) signal of 100 MHz bandwidth.